Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus

ABSTRACT

The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device includes a photodiode as a photoelectric conversion unit, a transfer gate that reads out charges from the photodiode, a floating diffusion from which the charges of the photodiode are read by an operation of the transfer gate, and an amplifying transistor connected to the floating diffusion. More particularly, the amplifying transistor is of a fully-depleted type. Such an amplifying transistor includes an amplifier gate (gate electrode) extending in a direction perpendicular to convex strips formed by processing a surface layer of a semiconductor layer, for example.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a continuation application of U.S. patentapplication Ser. No. 17/735,246, filed May 3, 2022, which is acontinuation application of U.S. patent application Ser. No. 17/315,014,filed May 7, 2021 (now U.S. Pat. No. 11,343,455), which is acontinuation application of U.S. patent application Ser. No. 16/844,670,filed Apr. 9, 2020 (now U.S. Pat. No. 11,032,504), which is acontinuation application of U.S. patent application Ser. No. 16/055,377,filed Aug. 6, 2018 (now U.S. Pat. No. 10,645,321), which is acontinuation application of U.S. patent application Ser. No. 15/671,227,filed Aug. 8, 2017 (now U.S. Pat. No. 10,044,962), which is acontinuation application of U.S. patent application Ser. No. 15/146,099,filed May 4, 2016 (now U.S. Pat. No. 9,762,832), which is a continuationapplication of U.S. patent application Ser. No. 14/363,971, filed Jun.9, 2014 (now U.S. Pat. No. 9,363,451), which is a National Stage ofPCT/JP2012/081755, filed Dec. 7, 2012, and claims the priority fromprior Japanese Priority Patent Application JP 2011-277076 filed in theJapan Patent Office on Dec. 19, 2011. Each of the above-referencedapplications is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present technique relates to solid-state imaging devices,solid-state imaging device manufacturing methods, and electronicapparatuses, and more particularly, to a solid-state imaging devicehaving amplifying transistors in pixel drive circuits, a method ofmanufacturing the solid-state imaging device, and an electronicapparatus using the solid-state imaging device.

BACKGROUND ART

Among solid-state imaging devices, there are CMOS sensors. In a CMOSsensor that has pixel drive circuits for respective pixels, chargesconverted by the photoelectric conversion units of the respective pixelsare amplified by amplifying transistors (source followers) included inthe pixel drive circuits, and the amplified charges are output tovertical signal lines by a switching operation (see Non-Patent Document1 below).

CITATION LIST Non-Patent Document

-   Non-Patent Document 1: International Image Sensor Workshop 2007    (June 7-10, Ogunquit, Maine, USA), “Modeling of the Temporal Pixel    to Pixel Noise of CMOS Image Sensors”, pp. 219-222, [Search Date:    Dec. 15, 2011], the Internet address    (URL:http://www.imagesensors.org/Past%20Workshops/2007%20Workshop/2007%20Papers/056%20Leyrig/020et%20al.pdf)

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

In recent years, solid-state imaging devices have become smaller in sizeand higher in the degree of integration, and accordingly,miniaturization of the elements that constitute the pixel drive circuitshas been progressing. In CMOS sensors, however, RTS (Random TelegraphSignal) noise is generated due to miniaturization of amplifyingtransistors (source followers) as described in Non-Patent Document 1,and the noise forms blinking points that degrade displaycharacteristics.

In view of the above, the present technique aims to provide asolid-state imaging device that can prevent generation of RTS noise dueto miniaturization of amplifying transistors, and can achieve a smallersize and a higher degree of integration accordingly. The presenttechnique also aims to provide a method of manufacturing such asolid-state imaging device, and an electronic apparatus using such asolid-state imaging device.

Solutions to Problems

A solid-state imaging device according to the present technique forachieving the above objects includes: a photoelectric conversion unit; atransfer gate that reads out charges from the photoelectric conversionunit; a floating diffusion from which the charges of the photoelectricconversion unit are read by an operation of the transfer gate; and anamplifying transistor of a fully-depleted type that is connected to thefloating diffusion. More particularly, the amplifying transistor is of afully-depleted type. Such an amplifying transistor includes a gateelectrode extending in a direction perpendicular to convex strips formedby processing a surface layer of a semiconductor layer, for example.

A solid-state imaging device manufacturing method according to thepresent technique includes: forming convex strips by processing asurface layer of a semiconductor layer; forming a photoelectricconversion unit in the semiconductor layer; and forming a floatingdiffusion that is located in the surface layer of the semiconductorlayer and is in the vicinity of the photoelectric conversion unit. Themanufacturing method also includes: forming a transfer gate on thesurface of the semiconductor layer between the photoelectric conversionunit and the floating diffusion, and forming a gate interconnect that isconnected to the floating diffusion and extends in a directionperpendicular to the convex strips.

The present technique also provides an electronic apparatus thatincludes the above described solid-state imaging device.

In the solid-state imaging device having the above described structure,the amplifying transistor connected to the floating diffusion has afully-depleted structure that operates as a transistor withoutcontaining any impurity in the channel portion. Accordingly, generationof RTS (Random Telegraph Signal) noise due to fluctuations of thechannel impurity in amplifying transistors is prevented, and theamplifying transistors are miniaturized.

Effects of the Invention

As described above, according to the present technique, amplifyingtransistors of a fully-depleted type that can prevent generation of RTSnoise are used. Accordingly, further miniaturization of amplifyingtransistors is realized, and a reduction in size and an increase in thedegree of integration can be achieved in a solid-state imaging device.Also, a reduction in size can be achieved in an electronic apparatusthat uses such a solid-state imaging device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic view of an example structure of a solid-stateimaging device to which the present technique is applied.

FIG. 2 is a schematic view of an example structure of a pixel drivecircuit of a solid-state imaging device to which the present techniqueis applied.

FIG. 3 is a schematic plan view of principal components in the structureof a solid-state imaging device according to a first embodiment.

FIG. 4 is a cross-sectional view of the principal components in thestructure of the solid-state imaging device according to the firstembodiment.

FIGS. 5A, 5B, and 5C are (first) diagrams showing the process formanufacturing the solid-state imaging device according to the firstembodiment.

FIGS. 6A and 6B are (second) diagrams showing the process formanufacturing the solid-state imaging device according to the firstembodiment.

FIGS. 7A and 7B are (third) diagrams showing the process formanufacturing the solid-state imaging device according to the firstembodiment.

FIG. 8 is a schematic plan view of principal components in the structureof a solid-state imaging device according to a second embodiment.

FIG. 9 is a cross-sectional view of the principal components in thestructure of the solid-state imaging device according to the secondembodiment.

FIGS. 10A, 10B, and 10C are (first) diagrams showing the process formanufacturing the solid-state imaging device according to the secondembodiment.

FIGS. 11A, 11B, and 11C are (second) diagrams showing the process formanufacturing the solid-state imaging device according to the secondembodiment.

FIGS. 12A and 12B are (third) diagrams showing the process formanufacturing the solid-state imaging device according to the secondembodiment.

FIG. 13 is a schematic view of an example structure of an electronicapparatus according to a third embodiment.

MODES FOR CARRYING OUT THE INVENTION

Embodiments of the present technique are described in the followingorder, with reference to the accompanying drawings.

-   -   1. Outline of an example structure of a solid-state imaging        device according to an embodiment    -   2. First embodiment (an example including a fully-depleted        amplifying transistor and a sidewall transfer gate)    -   3. Second embodiment (an example including a fully-depleted        amplifying transistor and a photoelectric conversion unit having        a stack structure) 4. Third embodiment (an example of an        electronic apparatus using a solid-state imaging device)

In the respective embodiments, like components are denoted by likereference numerals, and the same explanation will not be made more thanonce.

1. Outline of an Example Structure of a Solid-State Imaging DeviceAccording to an Embodiment

FIG. 1 schematically shows the structure of a solid-state imaging deviceusing a MOS solid-state imaging device as an example of a solid-stateimaging device according to the present technique.

The solid-state imaging device 1 shown in this drawing has a pixel area4 in which pixels 3 each including a photoelectric conversion unit aretwo-dimensionally arranged on a surface of a supporting substrate 2.Each of the pixels 3 arranged in the pixel area 4 has a pixel circuitthat is formed with a photoelectric conversion unit, a floatingdiffusion, a read gate, and other transistors (so-called MOStransistors), as will be described below. In some cases, two or morepixels 3 share part of the pixel circuit.

In the regions surrounding the pixel area 4, peripheral circuits such asvertical drive circuits 5, column signal processing circuits 6,horizontal drive circuits 7, and a system control circuit 8 areprovided.

The vertical drive circuits 5 are formed with shift registers, forexample, select pixel drive lines 9, supply a pulse for driving thepixels 3 to the selected pixel drive lines 9, and drive the pixels 3arranged in the pixel area 4 on a row-by-row basis. That is, thevertical drive circuits 5 selectively scan the respective pixelsarranged in the pixel area 4 on a row-by-row basis sequentially in thevertical direction. The vertical drive circuits 5 then supply pixelsignals based on signal charges generated in accordance with the amountsof light received by the respective pixels 3, to the column signalprocessing circuits 6 through vertical signal lines 10 that are arrangedin a direction perpendicular to the pixel drive lines 9.

The column signal processing circuits 6 are provided for the respectivecolumns of the pixels, for example, and perform, on a column-by-columnbasis, signal processing such as denoising on signals that are outputfrom the pixels 3 of one row. Specifically, the column signal processingcircuits 6 perform signal processing, such as correlated double sampling(CDS) for removing fixed pattern noise inherent to pixels, signalamplification, and analog-digital (AD) conversion.

The horizontal drive circuits 7 are formed with shift registers, forexample, and sequentially output horizontal scan pulses, to sequentiallyselect the respective column signal processing circuits 6, and cause therespective column signal processing circuits 6 to output pixel signals.

The system control circuit 8 receives an input clock and data indicatingan operation mode, and outputs data such as internal information aboutthe solid-state imaging device 1. Specifically, based on a verticalsynchronization signal, a horizontal synchronization signal, and amaster clock, the system control circuit 8 generates a clock signal anda control signal that set standards for operations of the vertical drivecircuits 5, the column signal processing circuits 6, the horizontaldrive circuits 7, and the like. Those signals are then input to thevertical drive circuits 5, the column signal processing circuits 6, thehorizontal drive circuits 7, and the like.

The above described peripheral circuits 5 through 8 and the pixelcircuits provided in the pixel area 4 constitute the drive circuits fordriving the respective pixels. The peripheral circuits 5 through 8 maybe located in such positions as to be stacked on the pixel area 4.

FIG. 2 is an equivalent circuit diagram of the pixel circuit provided ineach of the pixels 3. Each of the pixels 3 in this example includes aphotodiode PD that forms a photoelectric conversion unit, and four pixeltransistors. The four pixel transistors are formed with a transfertransistor Tr1, a reset transistor Tr2, an amplifying transistor Tr3,and a select transistor Tr4. Here, the transfer transistors Tr1 throughTr4 are n-channel MOS transistors, for example.

The photodiode PD is connected to the transfer transistor Tr1. Thetransfer transistor Tr1 is connected to the reset transistor Tr2 via afloating diffusion portion FD. Signal charges (electrons in this case)that are photoelectrically converted by the photodiode PD and are storedtherein are transferred to the floating diffusion portion FD when atransfer pulse φTRG is applied to the gate (transfer gate) of thetransfer transistor Tr1. The transfer pulse φTRG is supplied through oneof the pixel drive lines 9.

The floating diffusion portion FD is connected to the gate of theamplifying transistor Tr3. The drain of the amplifying transistor Tr3and the drain of the reset transistor Tr2 are connected to a powersupply VDD. Here, the source of the reset transistor Tr2 (or the drainof the transfer transistor Tr1) serves as the floating diffusion portionFD. Before signal charges are transferred from the photodiode PD to thefloating diffusion portion FD, a reset pulse φRST is applied to thereset gate, to reset the potential of the floating diffusion portion FD.The reset pulse φRST is supplied through one of the pixel drive lines 9.

The source of the amplifying transistor Tr3 is connected to the drain ofthe select transistor Tr4, and the source of the select transistor isconnected to the vertical signal line 10. A select pulse φSEL is appliedto the gate of the select transistor Tr4, so that the select transistorTr4 is put into an ON state, and the pixel 3 is selected. The selectpulse φSEL is supplied through one of the pixel drive lines 9. Theamplifying transistor Tr3 outputs the potential of the floatingdiffusion portion FD reset by the reset transistor Tr2 as the resetlevel to the vertical signal line 10 via the select transistor Tr4.After signal charges are transferred by the transfer transistor Tr1, theamplifying transistor Tr3 outputs the potential of the floatingdiffusion portion FD as the signal level to the vertical signal line 10via the select transistor Tr4. Alternatively, the select transistor Tr4may be connected between the power supply VDD and the drain of theamplifying transistor Tr3. In that case, the source of the amplifyingtransistor Tr3 is connected to the vertical signal line 10.

2. First Embodiment

<Structure of a Solid-State Imaging Device>

(Example Including a Fully-Depleted Amplifying Transistor and a SidewallTransfer Gate)

FIG. 3 is a schematic plan view of principal components in the structureof a solid-state imaging device 1-1 according to a first embodiment.FIG. 4 shows cross-sections that are taken along the A-A section lineand the B-B section line defined in FIG. 3 . FIGS. 3 and 4 show theportions that are equivalent to the portions from the photodiode PD tothe floating diffusion FD and the portion of the amplifying transistorTr3 shown in FIG. 2 . Referring to those drawings, the structure of thesolid-state imaging device 1-1 according to the first embodiment isdescribed below.

As shown in FIGS. 3 and 4 , the solid-state imaging device 1-1 accordingto the first embodiment has a photodiode PD forming a photoelectricconversion unit in a semiconductor layer 11. Gate electrodes including atransfer gate TG and the amplifier gate AG of the amplifying transistorTr3 are placed on a principal plane (surface) of the semiconductor layer11 via a gate insulating film 13. An interconnect layer in whichinterconnects 19 insulated by an interlayer insulating film 17 arestacked to form a multilayer film is placed over the upper layers ofthose gate electrodes.

The other principal plane of the semiconductor layer 11 serves as alight receiving surface A for the photodiode PD, and optical layers suchas color filters (not shown) and an on-chip lens 23 are placed on thelight receiving surface A via a protective insulating film 21. With thisstructure, the solid-state imaging device 1-1 is of a back-illuminatedtype, having the light receiving surface A in the principal plane on theopposite side from the interconnect layer.

The respective components will be described below in detail in thefollowing order: the semiconductor layer 11, the photodiode PD forming aphotoelectric conversion unit, the floating diffusion FD, the transfergate TG, and the amplifying transistor Tr3.

[Semiconductor Layer 11]

The semiconductor layer 11 is formed with an intrinsic semiconductor ofsingle-crystal silicon, for example, and the entire surface of the lightreceiving surface A is covered with an interface region 25 formed byintroducing a p-type impurity into the semiconductor layer 11. On thesurface on the opposite side of the semiconductor layer 11 from thelight receiving surface A, concave portions 31 adjacent to therespective photodiodes PD are formed. On the surface of thesemiconductor layer 11, convex strips 33 are arranged in parallel in theformation region of the amplifying transistor Tr3. In this example,three convex strips 33 are arranged in parallel.

The respective convex strips 33 are formed by removing the portionsaround the respective convex strips 33 in the semiconductor layer 11.The height h of the convex strips 33 is the same as the depth d of theconcave portions 31, and the steps formed by the convex strips 33 may beequal to the steps formed by the concave portions 31. Each of the convexstrips 33 has a predetermined width w1 in a direction perpendicular tothe extending direction thereof.

In a case where two or more photodiodes PD share one pixel drive circuitthat includes a floating diffusion FD and an amplifying transistor Tr3,one concave portion 31 is formed adjacent to the two or more photodiodesPD.

[Photodiode (Photoelectric Conversion Unit) PD]

The photodiode PD forming a photoelectric conversion unit is formed withthe pn junction between a charge storage region 35 that is an n-typeimpurity region in the semiconductor layer 11 and a p-type impurityregion in contact with the charge storage region 35. In this example,the n-type charge storage region 35 is provided between the p-typeinterface region 25 located on the side of the light receiving surface Aof the semiconductor layer 11 and a p-type interface region 37 formed onthe surface layer of the semiconductor layer 11 on the opposite sidefrom the p-type interface region 25. The pn junction between thoseregions forms the photodiode PD.

Such a photodiode PD is provided in such a manner that the chargestorage region 35 is exposed through a sidewall of the concave portion31 of the semiconductor layer 11. The charge storage region 35 ispreferably also exposed through the bottom portion of the concaveportion 31. Accordingly, the portion of the charge storage region 35closer to the light receiving surface A than to the bottom portion ofthe concave portion 31 can also be easily affected by the charges fromthe transfer gate TG.

[Floating Diffusion FD]

The floating diffusion FD is the portion from which charges stored inthe charge storage region 35 of the photodiode PD are read by anoperation of the transfer gate TG. Such a floating diffusion FD issurrounded by a p-type well region 39 exposed through the bottom portionof the concave portion 31, and faces the bottom portion of the concaveportion 31. The p-type well region 39 is in contact with the n-typecharge storage region 35 forming the photodiode PD. Accordingly, thep-type well region 39 is located between the floating diffusion FD andthe n-type charge storage region 35. The p-type well region 39 isdesigned to reach the p-type interface region 25 formed on the side ofthe light receiving surface A of the semiconductor layer 11.

[Transfer Gate TG]

The transfer gate TG is the gate electrode for reading out the chargesstored in the charge storage region 35 of the photodiode PD to thefloating diffusion FD. Such a transfer gate TG is designed to extendalong a sidewall of the concave portion 31 to which the charge storageregion 35 of the photodiode PD is exposed via the gate insulating film13, and is formed as a “sidewall transfer gate”. More specifically, thetransfer gate TG is designed to extend from the surface of thesemiconductor layer 11 to a sidewall of the concave portion 31, andfurther extend from the sidewall of the concave portion 31 to the bottomportion of the concave portion 31. At the bottom portion of the concaveportion 31, the transfer gate TG is provided on the well region 39, andthe floating diffusion FD is exposed through the transfer gate TG. Sucha transfer gate TG is made of polysilicon, for example.

[Amplifying Transistor Tr3]

The amplifying transistor Tr3 is a transistor connected to the floatingdiffusion FD, and is characteristically formed as a transistor of afully-depleted type in this example. Such an amplifying transistor Tr3has a channel that is formed with convex strips 33 arranged in parallel.The amplifying transistor Tr3 also includes a gate electrode (or theamplifier gate AG) extending in a direction perpendicular to thoseconvex strips 33. In the amplifying transistor Tr3, a source 43 s and adrain 43 d formed with n-type impurity regions are further provided atboth sides of the amplifier gate AG in the extending direction of theconvex strips 33.

Here, each of the convex strips 33 constituting the channel is designedto function as a transistor of a fully-depleted type by adjusting thewidth w1 in the direction perpendicular to the extending directionthereof and the impurity density in the portion of the convex strip 33.The width w1 of each of the convex strips 33 is on the order of severaltens of nm, for example. A p-type well region 41 is formed in theportion of the semiconductor layer 11 located under the convex strips33. The impurity density in the convex strips 33 is such that theamplifying transistor Tr3 can function as a transistor of afully-depleted type, and a low-density channel impurity may be containedas an impurity. In view of this, as long as the amplifying transistorTr3 can function as a transistor of a fully-depleted type, the convexstrips 33 may be formed with so-called “intrinsic semiconductor”portions, and constitute an intrinsic channel.

In such an amplifying transistor Tr3, the length of the portion in whichthe amplifier gate AG is placed along the convex strips 33 in thedirection perpendicular to the extending direction of the convex strips33 is the channel width W. That is, the channel width W is calculated asW=(2×h+w1)×3], where h represents the height and w1 represents the widthof each of the convex strips 33, and the number of the convex strips 33is three.

In the example shown in the drawing, the convex strips 33 are formed onthe well region 41. However, the well region 41 may exist inside theconvex strips 33 at the lower portions of the convex strips 33, so thatdevice separation of the amplifying transistor Tr3 is assured. In thiscase, the portions of the convex strips 33 minus the well region 41serve as the channel. Therefore, the height h of the convex strips 33related to the channel width W becomes smaller by the height of the wellregion 41 existing in the convex strips 33.

If leakage current is ignorable, a space may be formed between the wellregion 41 and the convex strips 33, so as to increase the channel widthW of the amplifying transistor Tr3. In this case, the width w2 betweeneach two convex strips 33 and the extension width of the amplifier gateAG at either end of the convex strips 33 are added to the channel widthW.

In the amplifying transistor Tr3, the width L of the amplifier gate AGin the extending direction of the convex strips 33 is the channel lengthL.

The amplifying transistor Tr3 described above has its amplifier gate AGconnected to the floating diffusion FD via the interconnects 19 andconnection holes not shown in the drawings.

<Effects of the Solid-State Imaging Device According to the FirstEmbodiment>

In the solid-state imaging device 1-1 described above, a fully-depletedstructure that functions as a transistor even if the impurity density inthe channel portion is low is used as the amplifying transistor Tr3.With this structure, generation of RTS noise due to random dopantfluctuations (RDF) of the channel impurity can be prevented particularlyin the miniaturized amplifying transistor Tr3. Accordingly, theamplifying transistor Tr3 can be further miniaturized, and the imagingarea in which the amplifying transistor Tr3 is located can be madesmaller. As a result, a reduction in size and an increase in the degreeof integration can be achieved in the solid-state imaging device 1-1that uses the amplifying transistor Tr3.

Furthermore, in the solid-state imaging device 1-1 according to thefirst embodiment, the amplifying transistor Tr3 is designed as a finstructure in which the amplifier gate AG is positioned so as to extendin a direction perpendicular to the convex strips 33 formed in thesemiconductor layer 11. In this case, the convex strips 33 serve as thechannel portion in the amplifying transistor Tr3. As described above,the channel width W in the amplifying transistor Tr3 is the length ofthe junction between the convex strips 33 and the amplifier gate AG viathe gate insulating film 13 in the direction perpendicular to the convexstrips 33. Accordingly, the channel width W can be increased in relationto the area occupied by the amplifying transistor Tr3. The effect toincrease the channel width W is greater where the number of the convexstrips 33 to which the amplifier gate AG extends perpendicularly islarger. Accordingly, the area occupied by the amplifying transistor Tr3can be made smaller with respect to the set value of the channel width Wrequired for the amplifying transistor Tr3.

Further, in the amplifying transistor Tr3 of the fully-depleted type,the conversion efficiency is increased as the amplifier gain isincreased. Accordingly, the amplifying transistor Tr3 can beminiaturized in relation to the required conversion efficiency.

With the above characteristics, the imaging area can be made smaller,and a reduction in size and an increase in the degree of integration canbe achieved in the solid-state imaging device 1-1.

Also, in the solid-state imaging device 1-1 according to the firstembodiment, the transfer gate TG is placed along a sidewall of theconcave portion 31 through which the charge storage region 35 of thephotodiode PD is exposed, so that charges collected from a wider area inthe charge storage region 35 are transferred to the floating diffusionFD. Furthermore, the floating diffusion FD is provided in the bottomportion of the concave portion 31, so that the potential gradientbetween the n-type charge storage region 35 and the floating diffusionFD is easily formed. Accordingly, a charge flow reversal from thefloating diffusion FD to the charge storage region 35 can be certainlyprevented. Also, an impurity can be introduced into the transfer gate TGmade of polysilicon by ion implantation from an oblique direction.Therefore, depletion of the transfer gate TG can also be prevented. Withthe above characteristics, the efficiency of charge transfer from thecharge storage region 35 to the floating diffusion FD can be increased.

<Method of Manufacturing the Solid-State Imaging Device>

Referring now to the cross-sectional process diagrams shown in FIGS. 5A,5B, 5C, 6A, 6B, 7A, 7B, and 8 , a method of manufacturing thesolid-state imaging device 1-1 having the above described structure isdescribed.

[FIG. 5A]

First, as shown in FIG. 5A, a SOI (silicon on insulator) substratehaving the semiconductor layer 11 formed thereon via an oxide film 103is prepared on a supporting substrate 101. The oxide film 103 is made ofsilicon oxide, for example, and the semiconductor layer 11 is made of anintrinsic semiconductor of silicon. The face of the semiconductor layer11 facing the oxide film 103 is the light receiving surface A. The faceon the opposite side from the light receiving surface A is the surface.

[FIG. 5B]

As shown in FIG. 5B, the interface region 25 having a p-type impurityimplanted therein is formed on the entire surface of the interface layeron the side of the light receiving surface A of the semiconductor layer11. The interface region 37 having a p-type impurity implanted thereinis formed in a position including the photodiode formation region a inthe surface layer on the opposite side of the semiconductor layer 11from the light receiving surface A. At this point, the p-type interfaceregion 37 is not formed in the amplifying transistor formation region b.

Further, the charge storage region 35 having an n-type impurityimplanted therein is formed between the p-type interface region 25 andthe p-type interface region 37 in the photodiode formation region a inthe semiconductor layer 11, to obtain the photodiode PD. The well region39 having a p-type impurity implanted therein is formed adjacent to thecharge storage region 35 and the interface region 25 in a deep region onthe side of the light receiving surface A of the semiconductor layer 11.In the same procedure as above, the well region 41 having a p-typeimpurity implanted therein is also formed adjacent to the interfaceregion 25 in the amplifying transistor formation region b in thesemiconductor layer 11 and in a deep region on the side of the lightreceiving surface A of the semiconductor layer 11.

The regions having the respective impurities implanted therein areformed by using ion implantation followed by annealing, and, ifnecessary, epitaxial growth. However, the regions may be formed by ionimplantation in any order. Also, the ion implantation for forming theinterface region 37, the n-type charge storage region 35, and the wellregions 39 and 41 is performed with respective resist patterns servingas masks.

[FIG. 5C]

As shown in FIG. 5C, the concave portion 31 and the convex strips 33 areformed on the surface layer on the opposite side of the semiconductorlayer 11 from the light receiving surface A in a single procedure. Theconcave portion 31 is formed in such a position that the n-type chargestorage region 35 is exposed through a sidewall thereof, and has such adepth d that the well region 39 is exposed through the bottom portion.

In the amplifying transistor formation region b, the convex strips 33are formed to have a height h (=d) by removing the intrinsicsemiconductor portions surrounding the convex strips 33 in thesemiconductor layer 11. In this situation, the convex strips 33 maypenetrate into the well region 41. Also, a space may be formed betweenthe convex strips 33 and the well region 41, as long as leakage currentis ignorable. In a case where a space is formed between the convexstrips 33 and the well region 41, however, the well region 39 is notexposed through the bottom portion of the concave portion 31 formed inthe same procedure as the convex strips 33. Therefore, a p-type impurityis selectively implanted into the bottom portion of the concave portion31, so that the well region 39 is formed to face the bottom portion ofthe concave portion 31.

The concave portion 31 and the convex strips 33 described above areformed by anisotropic etching, with a resist pattern being used as amask.

[FIG. 6A]

As shown in FIG. 6A, the transfer gate TG is formed along the sidewallof the concave portion 31 through which the charge storage region 35 ofthe photodiode PD is exposed, and the amplifier gate AG extending in thedirection perpendicular to the convex strips 33 is formed in theamplifying transistor formation region b. In this procedure, the gateinsulating film 13 is first formed on the exposed surface of thesemiconductor layer 11 by thermal oxidation, and a gate electrode filmmade of polysilicon, for example, is formed on the gate insulating film13. Patterning is then performed on the gate electrode film and the gateinsulating film 13 by anisotropic etching using a resist pattern as amask, to obtain the transfer gate TG and the amplifier gate AG.

[FIG. 6B]

As shown in FIG. 6B, the floating diffusion FD having an n-type impurityimplanted therein is then formed in the surface layer of the well region39 adjacent to the charge storage region 35. In this procedure, thefloating diffusion FD is formed by ion implantation followed byannealing, with a resist pattern and the transfer gate TG being used asa mask.

Also, as shown in FIG. 3 , the source 43 s and the drain 43 d that havean n-type impurity implanted therein are formed at the sides of theamplifier gate AG in the amplifying transistor formation region b. Inthis procedure, the source 43 s and the drain 43 d are formed by ionimplantation followed by annealing, with a resist pattern and theamplifier gate AG being used as a mask. In this manner, thefully-depleted amplifying transistor Tr3 having the convex strips 33 asthe channel is obtained.

The formation of the floating diffusion FD and the formation of thesource 43 s and the drain 43 d described above may be performed in asingle procedure.

[FIG. 7A]

As shown in FIG. 7A, a procedure for forming the interlayer insulatingfilm 17 on the semiconductor layer 11 in such a manner as to cover thetransfer gate TG and the amplifier gate AG and fill the grooves, aprocedure for forming connection holes (not shown) in the interlayerinsulating film 17, and a procedure for forming the interconnects 19 onthe interlayer insulating film 17 are carried out. After that, thoseprocedures are sequentially repeated, and the procedure for forming theinterlayer insulating film 17 is carried out at last. In this manner,the interconnect layer in which the interconnects 19 insulated by theinterlayer insulating film 17 are stacked to form a multilayer is formedon the surface on the opposite side of the semiconductor layer 11 fromthe light receiving surface A.

[FIG. 7B]

As shown in FIG. 7B, the supporting substrate 101 and the oxide film 103are removed from the side of the light receiving surface A of thesemiconductor layer 11, to expose the light receiving surface A of thesemiconductor layer 11.

[FIG. 4 ]

After the above procedures, the protective insulating film 21 is formedon the light receiving surface A of the semiconductor layer 11, ifnecessary, and the on-chip lens 23 is further formed, as shown in FIG. 4. Also, an antireflection film, a light shielding film, and color filterlayers not shown in the drawing are formed between the protectiveinsulating film 21 and the on-chip lens 23, if necessary. In thismanner, the solid-state imaging device 1-1 is completed.

<Effects of the Manufacturing Method According to the First Embodiment>

By the above described manufacturing method, the convex strips 33 thatserve as the channel portion of the amplifying transistor Tr3, and theconcave portion 31 in which the transfer gate TG is placed are formed ina single procedure. Also, the amplifier gate AG and the transfer gate TGare formed in a single procedure. Further, the floating diffusion FD,and the source 43 s and the drain 43 d are formed in a single procedure.Accordingly, the solid-state imaging device 1-1 according to the firstembodiment can be obtained in a simpler manner.

3. Second Embodiment

(Example Including a Fully-Depleted Amplifying Transistor and aPhotoelectric Conversion Unit with a Stack Structure)

FIG. 8 is a schematic plan view of principal components in the structureof a solid-state imaging device 1-2 according to a second embodiment.FIG. 9 shows cross-sections that are taken along the A-A section lineand the B-B section line defined in FIG. 8 . FIGS. 8 and 9 show theportions that are equivalent to the portions from the photodiode PDformed as a photoelectric conversion unit to the floating diffusion FD,and the portion of the amplifying transistor Tr3.

As shown in FIGS. 8 and 9 , in the solid-state imaging device 1-2according to the second embodiment, an exposed photodiode PD1 and anembedded photodiode PD2 are stacked and provided as a photoelectricconversion unit in a semiconductor layer 11. These photodiodes PD1 andPD2 are used as a photoelectric conversion unit for light with differentwavelength ranges from each other. Gate electrodes including transfergates TG1 and TG2, and the amplifier gate AG of an amplifying transistorTr3 are placed on a principal plane (surface) of the semiconductor layer11 via a gate insulating film 13, as in the first embodiment. Aninterconnect layer in which interconnects 19 insulated by an interlayerinsulating film 17 are stacked to form a multilayer film is placed overthe upper layers of those gate electrodes.

The other principal plane of the semiconductor layer 11 serves as alight receiving surface A for the photodiodes PD1 and PD2. On the lightreceiving surface A, another photoelectric conversion unit 51 isprovided in such a manner as to be stacked on the two photodiodes PD1and PD2 via a protective insulating film 21. This photoelectricconversion unit 51 is used as a photoelectric conversion unit for lightwith a different wavelength range from those of the above describedphotodiodes PD1 and PD2.

On the light receiving surface A, an on-chip lens 23 and the like areprovided as in the first embodiment, if necessary, in such a manner asto cover the photoelectric conversion unit 51. However, there is no needto provide color filters between the photoelectric conversion unit 51and the on-chip lens 23. With this structure, the solid-state imagingdevice 1-2 is of a back-illuminated type, having the light receivingsurface A in the principal plane on the opposite side from theinterconnect layer.

The respective components will be described below in detail in thefollowing order: the semiconductor layer 11, the exposed photodiode PD1,the embedded photodiode PD2, the photoelectric conversion unit 51, andthe amplifying transistor Tr3.

[Semiconductor layer 11]

The semiconductor layer 11 is made of n-type single-crystal silicon, forexample, and the entire surface of the light receiving surface A iscovered with an interface region 25 formed by introducing a p-typeimpurity into the semiconductor layer 11. On the surface on the oppositeside of the semiconductor layer 11 from the light receiving surface A,concave portions 31 adjacent to the exposed photodiode PD1 are formed.On the surface of the semiconductor layer 11, convex strips 33 arearranged in parallel in the formation region of the amplifyingtransistor Tr3. These convex strips 33 are the same as those of thefirst embodiment, having a height h that is equal to the depth d of theconcave portions 31, and a predetermined width w1 in a directionperpendicular to the extending direction thereof.

[Exposed Photodiode (Photoelectric Conversion Unit) PD1]

The exposed photodiode PD1 forming a photoelectric conversion unit is aphotoelectric conversion unit for light in the wavelength range of red,for example. This photodiode PD1 is formed with the pn junction betweena charge storage region 61 that is an n-type impurity region formed inthe semiconductor layer 11 and a p-type impurity region in contact withthe charge storage region 61. In this example, the n-type charge storageregion 61 is in contact with a p-type interface region 63 formed in thesurface layer on the opposite side of the semiconductor layer 11 fromthe light receiving surface A, and a p-type interface region 65 formedon a sidewall side of the concave portion 31. The pn junction betweenthose regions forms the photodiode PD1.

A floating diffusion FD1 is formed near the photodiode PD1. The floatingdiffusion FD1 is the portion from which charges stored in the chargestorage region 61 of the photodiode PD1 are read by an operation of thetransfer gate TG1. Such a floating diffusion FD1 is formed in thesurface layer of the semiconductor layer 11 in such a manner as to besurrounded by a p-type well region 67 located adjacent to the chargestorage region 61. In this situation, the p-type well region 67 islocated between the floating diffusion FD1 and the n-type charge storageregion 61. The p-type well region 67 is designed to reach the p-typeinterface region 25 formed on the side of the light receiving surface Aof the semiconductor layer 11.

The transfer gate TG1 for reading out the charges stored in the chargestorage region 61 of the photodiode PD1 to the floating diffusion FD1 isprovided between the photodiode PD1 and the floating diffusion FD1. Sucha transfer gate TG1 is placed on the portion of the well region 67located between the charge storage region 61 and the floating diffusionFD1 via the gate insulating film 13.

[Embedded Photodiode (Photoelectric Conversion Unit) PD2]

The exposed photodiode PD2 forming a photoelectric conversion unit is aphotoelectric conversion unit for light in the wavelength range of blue,for example. In this photodiode PD2, an n-type impurity region stackedon the n-type charge storage region 61 forming the photodiode PD1 servesas a charge storage region 71 in the semiconductor layer 11. In thisexample, the n-type charge storage region 71 is stacked on the n-typecharge storage region 61 via a separation region 73 formed with a p-typeimpurity region. The n-type charge storage region 71 is also located incontact with the p-type interface region 25 formed on the side of thelight receiving surface A of the semiconductor layer 11. The pn junctionbetween those regions forms the photodiode PD2.

Such a photodiode PD2 is designed to protrude toward the bottom faceside of the concave portion 31 of the semiconductor layer 11. In thiscase, in the bottom face of the concave portion 31, the n-type chargestorage region 71 is covered with the p-type separation region 73.

A floating diffusion FD2 is formed near the photodiode PD2. The floatingdiffusion FD2 is the portion from which charges stored in the chargestorage region 71 of the photodiode PD2 are read by an operation of thetransfer gate TG2. Such a floating diffusion FD2 is surrounded by ap-type well region 75 exposed through the bottom portion of the concaveportion 31, and faces the bottom portion of the concave portion 31. Thep-type well region 75 is in contact with the n-type charge storageregion 71 forming the photodiode PD2. Accordingly, the p-type wellregion 75 is located between the floating diffusion FD2 and the n-typecharge storage region 71. The p-type well region 75 is designed to reachthe p-type interface region 25 formed on the side of the light receivingsurface A of the semiconductor layer 11.

The transfer gate TG2 for reading out the charges stored in the chargestorage region 71 of the photodiode PD2 to the floating diffusion FD2 isalso provided between the photodiode PD2 and the floating diffusion FD2.Such a transfer gate TG2 is placed on the portion of the well region 75located between the charge storage region 71 and the floating diffusionFD2 via the gate insulating film 13.

[Photoelectric Conversion Unit 51]

The photoelectric conversion unit 51 is a photoelectric conversion unitfor light in the wavelength range of green, for example. On the lightreceiving surface A of the semiconductor layer 11, the photoelectricconversion unit 51 is provided in such a manner as to be stacked on thephotodiodes PD1 and PD2 via the protective insulating film 21. Thisphotoelectric conversion unit 51 includes pixel electrodes 55 formed onthe protective insulating film 21 by patterning, a photoelectricconversion film 57 formed on the pixel electrode 55, and a sharedelectrode 59 further formed on the photoelectric conversion film 57, andis formed at the portion where the photoelectric conversion film 57 isinterposed between the pixel electrodes 55 and the shared electrode 59.

Among those components, the pixel electrodes 55 are formed with atransparent conductive film that has been subjected to patterning so asto be divided on a pixel-by-pixel basis.

The photoelectric conversion film 57 is made of an organic photoelectricconversion material that photoelectrically converts light of a targetwavelength. The organic photoelectric conversion material thatphotoelectrically converts light of the wavelength of green may be anorganic photoelectric conversion material that contains a rhodamine dye,a merocyanine dye, or quinacridone, for example. The organicphotoelectric conversion material that photoelectrically converts lightof the wavelength of red may be an organic photoelectric conversionmaterial that contains a phthalocyanine dye. The organic photoelectricconversion material that photoelectrically converts light of thewavelength of blue may be an organic photoelectric conversion materialthat contains a coumarin dye, tris-8-hydroxyquinoline Al (Alq3), or amerocyanine dye, for example. The photoelectric conversion film 57 madeof such a material may be formed as a layer shared among all the pixels,or may be formed in a pattern that is divided on a pixel-by-pixel basis.

The shared electrode 59 is formed with a transparent conductive film,may be designed as a layer to be shared among all the pixels, and isconnected to a fixed potential. This shared electrode 59 may be formedin a pattern that is divided on a pixel-by-pixel basis. This sharedelectrode 59 may also be extended to the side of the surface of thesemiconductor layer 11 by a plug not shown in the drawings, and beconnected to a fixed potential via the interconnects 19 provided on thesurface side.

In the photoelectric conversion unit 51 having the above describedstructure, each of the pixel electrodes 55 is extended to the oppositesurface side of the semiconductor layer 11 from the light receivingsurface A by a plug not shown in the drawings, and is in contact withanother n-type charge storage region 53 shown only in the plan view inFIG. 8 . The plugs may be formed with impurity regions, and in thiscase, are of the n-type, which is the same as the type of the chargestorage region 53.

Although shown only in the schematic plan view in FIG. 8 , anotherfloating diffusion FD3 located near the charge storage region 53 isformed in the surface layer of the semiconductor layer 11. The floatingdiffusion FD3 is the portion from which charges extracted from the lowerelectrode of the photoelectric conversion unit 51 and stored in thecharge storage region 53 are read by an operation of a transfer gateTG3. Such a floating diffusion FD3 is formed in the surface layer of thesemiconductor layer 11 in such a manner as to be surrounded by a p-typewell region (not shown) located adjacent to the charge storage region53. In this situation, the p-type well region is located between thefloating diffusion FD3 and the n-type charge storage region 53.

The transfer gate TG3 for reading out the charges stored in the chargestorage region 53 to the floating diffusion FD3 is provided between thecharge storage region 53 and the floating diffusion FD3. Such a transfergate TG3 is placed on the portion of the well region located between thecharge storage region 53 and the floating diffusion FD3 via a gateinsulating film. Alternatively, the charge storage region 53, thefloating diffusion FD3, and the transfer gate TG3 may be located in thebottom portion of the concave portion 31.

[Amplifying Transistor Tr3]

The amplifying transistor Tr3 is a transistor that is connected to therespective floating diffusions FD1, FD2, and FD3. As in the firstembodiment, the amplifying transistor Tr3 used in this embodiment ischaracteristically formed as a transistor of a fully-depleted type, andhas the same structure as that of the first embodiment. Therefore,detailed explanation thereof is not repeated herein.

The amplifying transistor Tr3 described above has its amplifier gate AGconnected to the floating diffusions FD1, FD2, and FD3 via theinterconnects 19 and connection holes not shown in the drawings. Theconnections between the amplifying transistor Tr3 and the floatingdiffusions FD1, FD2, and FD3 may have one-to-one correspondence, or thefloating diffusions FD1, FD2, and FD3 may be connected to a singleamplifying transistor Tr3. Alternatively, floating diffusions located indifferent pixels from one another may be connected to a singleamplifying transistor Tr3.

<Effects of the Solid-State Imaging Device According to the SecondEmbodiment>

In the solid-state imaging device 1-2 described above, a fully-depletedstructure that functions as a transistor even if the impurity density inthe channel portion is low is used as the amplifying transistor Tr3, asin the first embodiment. Accordingly, as in the first embodiment, theamplifying transistor Tr3 can be further miniaturized, and a reductionin size and an increase in the degree of integration can be achieved inthe solid-state imaging device 1-2 that uses the amplifying transistorTr3.

In the solid-state imaging device 1-2 according to the secondembodiment, the amplifying transistor Tr3 is also designed as a finstructure in which the amplifier gate AG is positioned so as to extendin the direction perpendicular to the convex strips 33 formed in thesemiconductor layer 11. Accordingly, as in the first embodiment, thearea occupied by the amplifying transistor Tr3 can be reduced inrelation to the set value of the channel width W required for theamplifying transistor Tr3. With that, the imaging area can be madesmaller, and a reduction in size and an increase in the degree ofintegration can be achieved in the solid-state imaging device 1-2.

Furthermore, in the solid-state imaging device 1-2 according to thesecond embodiment, the photodiodes PD1 and PD2 and the photoelectricconversion unit 51 are provided as photoelectric conversion units forlight of different wavelength ranges from one another, and are stackedin one pixel. Accordingly, the photodiodes PD1 and PD2 and thephotoelectric conversion unit 51 are located at the depths (heights)corresponding to the respective wavelength ranges, so that wavelengthseparation can be performed without light loss caused by use of colorfilters. Thus, higher sensitivity and higher area efficiency can beachieved.

<Method of Manufacturing the Solid-State Imaging Device>

Referring now to the cross-sectional process diagrams shown in FIGS.10A, 10B, 10C, 11A, 11B, 11C, 12A, and 12B, a method of manufacturingthe solid-state imaging device 1-2 having the above described structureis described.

[FIG. 10A]

First, as shown in FIG. 10A, a SOI (silicon on insulator) substratehaving the semiconductor layer 11 formed thereon via an oxide film 103is prepared on a supporting substrate 101. The oxide film 103 is made ofsilicon oxide, for example, and the semiconductor layer 11 is made ofn-type silicon. The face of the semiconductor layer 11 facing the oxidefilm 103 is the light receiving surface A. The face on the opposite sidefrom the light receiving surface A is the surface.

[FIG. 10B]

As shown in FIG. 10B, the interface region 25 having a p-type impurityimplanted therein is formed on the entire surface of the interface layeron the side of the light receiving surface A of the semiconductor layer11. The interface region 63 having a p-type impurity implanted thereinis formed in a position including the photodiode formation region a inthe surface layer on the opposite side of the semiconductor layer 11from the light receiving surface A. At this point, the p-type interfaceregion 63 is not formed in the amplifying transistor formation region b.

Further, in the photodiode formation region a in the semiconductor layer11, the n-type charge storage region 71, the p-type separation region73, and the n-type charge storage region 61 are formed in this orderfrom the side of the light receiving surface A. The n-type chargestorage region 61 is formed in such a manner as to be in contact withthe p-type interface region 63. As a result, the exposed photodiode PD1and the embedded photodiode PD2 that are separated by the p-typeseparation region 73 and are stacked in the semiconductor layer 11 areobtained.

On one side of the photodiode formation region a in the semiconductorlayer 11, the p-type well region 67 is formed between the p-typeinterface region 63 and the p-type interface region 25. On the otherside of the photodiode formation region a in the semiconductor layer 11,the p-type well region 75 is formed between the p-type separation region73 and the p-type interface region 25. In the same procedure as theformation of the well region 75, the well region 41 having a p-typeimpurity implanted therein is also formed in the amplifying transistorformation region b in the semiconductor layer 11 and in a deep region onthe side of the light receiving surface A of the semiconductor layer 11.The well region 41 is formed in contact with the interface region 25.

Although not shown in the drawings, a plug having an n-type impurityimplanted therein, for example, is formed so as to penetrate into thesemiconductor layer 11 at a location not overlapping with the photodiodeformation region a, and the n-type charge storage region 53 (see FIG. 8) connected to the plug is further formed in the surface layer of thesemiconductor layer 11. This plug is not necessarily formed with animpurity region, and may be formed by filling an insulator-coatedconnection hole with a conductive material such as tungsten W.

The regions having impurities of the respective conductivity typesimplanted therein are formed by using ion implantation followed byannealing, and, if necessary, epitaxial growth. However, the regions maybe formed by ion implantation in any order. Also, the ion implantationfor forming the regions other than the interface region 25 is performedwith respective resist patterns serving as masks.

[FIG. 10C]

As shown in FIG. 10C, the concave portion 31 and the convex strips 33are formed on the surface layer on the opposite side of thesemiconductor layer 11 from the light receiving surface A in a singleprocedure. The concave portion 31 is formed in such a position that then-type charge storage region 61 is exposed through a sidewall thereof,and has such a depth d that the well region 75 is exposed through thebottom portion. At this point, the portion of the charge storage region71 covered with the separation region 73 may be exposed through thebottom portion of the concave portion 31.

In the amplifying transistor formation region b, the convex strips 33are formed to have a height h (=d) by removing the portions of thesemiconductor layer 11 surrounding the convex strips 33. In thissituation, the convex strips 33 may penetrate into the well region 41.Also, a space may be formed between the convex strips 33 and the wellregion 41, as long as leakage current is ignorable. In a case where aspace is formed between the convex strips 33 and the well region 41,however, the well region 75 is not exposed through the bottom portion ofthe concave portion 31 formed in the same procedure as the convex strips33. Therefore, a p-type impurity is selectively implanted into thebottom portion of the concave portion 31, so that the well region 75 isformed to face the bottom portion of the concave portion 31.

The concave portion 31 and the convex strips 33 described above areformed by anisotropic etching, with a resist pattern being used as amask.

[FIG. 11A]

As shown in FIG. 11A, the p-type interface region 65 is then formed insuch a manner as to cover the n-type charge storage region 61 exposedthrough a sidewall of the concave portion 31. The formation of theinterface region 65 located on a sidewall is performed by ionimplantation from an oblique direction, followed by annealing, forexample. If necessary, ion implantation is also performed with the useof a mask.

[FIG. 11B]

As shown in FIG. 11B, the transfer gate TG1 is formed on the surface ofthe semiconductor layer 11 at a location adjacent to the charge storageregion 61 of the photodiode PD1, and the transfer gate TG2 is formed inthe bottom portion of the concave portion 31 at a location adjacent tothe charge storage region 71 of the photodiode PD2. In the sameprocedure as above, the amplifier gate AG extending in the directionperpendicular to the convex strips 33 is also formed in the amplifyingtransistor formation region b. In the same procedure as above, thetransfer gate TG3 not shown in this drawing is further formed at alocation that does not overlap with the photodiode formation region a.

In this procedure, the gate insulating film 13 is first formed on theexposed surface of the semiconductor layer 11 by thermal oxidation, anda gate electrode film made of polysilicon, for example, is formed on thegate insulating film 13. Patterning is then performed on the gateelectrode film and the gate insulating film 13 by anisotropic etchingusing a resist pattern as a mask, to obtain the transfer gates TG1, TG2,and TG3, and the amplifier gate AG.

[FIG. 11C]

As shown in FIG. 11C, the floating diffusion FD1 having an n-typeimpurity implanted therein is then formed in the surface layer of thewell region 67 adjacent to the charge storage region 61. Further, thefloating diffusion FD2 having an n-type impurity implanted therein isformed in the surface layer of the well region 75 adjacent to the chargestorage region 71 in the bottom portion of the concave portion 31. Inthe same procedure as above, the floating diffusion FD3 shown in FIG. 8is also formed at a location close to the charge storage region 53.

In this procedure, the floating diffusions FD1, FD2, and FD3 are formedby ion implantation followed by annealing, with resist patterns and thetransfer gates TG1, TG2, and TG3 being used as masks.

Also, as shown in FIG. 8 , the source 43 s and the drain 43 d that havean n-type impurity implanted therein are formed at the sides of theamplifier gate AG in the amplifying transistor formation region b. Inthis procedure, the source 43 s and the drain 43 d are formed by ionimplantation followed by annealing, with a resist pattern and theamplifier gate AG being used as a mask. In this manner, thefully-depleted amplifying transistor Tr3 having the convex strips 33 asthe channel is obtained.

The formation of the floating diffusions FD1, FD2, and FD3, and theformation of the source 43 s and the drain 43 d described above may beperformed in a single procedure.

[FIG. 12A]

As shown in FIG. 12A, a procedure for forming the interlayer insulatingfilm 17 on the semiconductor layer 11 in such a manner as to cover thetransfer gates TG1 and TG2 as well as the amplifier gate AG and fill thegrooves, a procedure for forming connection holes (not shown) in theinterlayer insulating film 17, and a procedure for forming theinterconnects 19 on the interlayer insulating film 17 are carried out.After that, those procedures are sequentially repeated, and theprocedure for forming the interlayer insulating film 17 is carried outat last. In this manner, the interconnect layer in which theinterconnects 19 insulated by the interlayer insulating film 17 arestacked to form a multilayer is formed on the surface on the oppositeside of the semiconductor layer 11 from the light receiving surface A.

[FIG. 12B]

As shown in FIG. 12B, the supporting substrate 101 and the oxide film103 are removed from the side of the light receiving surface A of thesemiconductor layer 11, to expose the light receiving surface A of thesemiconductor layer 11.

[FIG. 9 ]

After that, as shown in FIG. 9 , the protective insulating film 21 isformed on the light receiving surface A of the semiconductor layer 11,and connection holes to reach the plugs not shown in the drawing areformed in the protective insulating film 21. The pixel electrodes 55made of a transparent conductive material are then formed on theprotective insulating film 21 by patterning. At this point, therespective pixel electrodes 55 are formed in such a manner as to beconnected to the plugs via the connection holes. As a result, therespective pixel electrodes 55 are connected to the charge storageregion 53 (see FIG. 8 ) via the plugs.

A separation insulating film 81 for dividing the pixel electrodes 55 isthen formed by patterning in such a manner as to cover the peripheralregions of the pixel electrodes 55. The photoelectric conversion film 57made of an organic photoelectric conversion material is then formed overthe pixel electrodes 55, and the shared electrode 59 made of atransparent conductive material is further formed for all the pixels.

After that, an insulating film 83 is formed on the shared electrode 59,and the on-chip lens 23 is formed thereon. Also, an antireflection filmand a light shielding film that are not shown in the drawing are formedbetween the shared electrode 59 and the on-chip lens 23, if necessary.In this manner, the solid-state imaging device 1-2 is completed.

<Effects of the Manufacturing Method According to the Second Embodiment>

By the above described manufacturing method, the convex strips 33 thatserve as the channel portion of the amplifying transistor Tr3, and theconcave portion 31 accommodating the floating diffusion FD2corresponding to the embedded photodiode PD2 and the transfer gate TG2are formed in a single procedure. Also, the amplifier gate AG and thetransfer gates TG1, TG2, and TG3 are formed in a single procedure.Further, the floating diffusions FD1, FD2, and FD3, and the source 43 sand the drain 43 d are formed in a single procedure. Accordingly, thesolid-state imaging device 1-2 according to the second embodiment can beobtained in a simpler manner.

In the first and second embodiments described above, a structure havingthe amplifier gate AG that extends in the direction perpendicular to theconvex strips 33 is used as the amplifying transistor Tr3 of afully-depleted type. However, some other structure, such as a FD (FullyDepleted)-SOI, may be used as the fully-depleted amplifying transistorTr3 in a solid-state imaging device according to the present technique.

4. Third Embodiment

(Examples of Electronic Apparatuses Using Solid-State Imaging Devices)

Solid-state imaging devices according to the present technique describedin the above embodiments can be used as solid-state imaging devices forelectronic apparatuses, such as camera systems like a digital camera anda video camera, portable telephone devices having imaging functions, andother apparatuses having imaging functions.

FIG. 13 is a diagram showing the structure of a camera that includes asolid-state imaging device as an example electronic apparatus accordingto the present technique. The camera according to this embodiment is avideo camera that is capable of capturing a still image or a movingimage. This camera 91 includes a solid-state imaging device 1, anoptical system 93 that guides incident light to the light receivingsensor unit of the solid-state imaging device 1, a shutter device 94, adrive circuit 95 that drives the solid-state imaging device 1, and asignal processing circuit 96 that process an output signal of thesolid-state imaging device 1.

The solid-state imaging device 1 is a solid-state imaging device havingthe structure described in the first or second embodiment. The opticalsystem (an optical lens) 93 gathers image light (incident light) from anobject onto the imaging surface of the solid-state imaging device 1. Onthis imaging surface, pixels are arranged, and the incident light fromthe optical system 93 is guided to the photoelectric conversion regionof the solid-state imaging elements forming the pixels. As a result,signal charges are stored in the photoelectric conversion region of thesolid-state imaging device 1 for a certain period of time. Such anoptical system 93 may be an optical lens system formed with opticallenses. The shutter device 94 controls the period to emit light to thesolid-state imaging device 1 and the period to shield light. The drivecircuit 95 supplies a drive signal to the solid-state imaging device 1and the shutter device 94, and controls the solid-state imaging device 1to output a signal to the signal processing circuit 96 and the shutterdevice 94 to perform a shutter operation in accordance with the supplieddrive signal (a timing signal). That is, the drive circuit 95 performsan operation to transfer a signal from the solid-state imaging device 1to the signal processing circuit 96 by supplying a drive signal (timingsignal). The signal processing circuit 96 performs various kinds ofsignal processing on the signal transferred from the solid-state imagingdevice 1. The video signal subjected to the signal processing is storedinto a storage medium such as a memory, or is output to a monitor.

The above described electronic apparatus according to this embodimentincludes a solid-state imaging device that is small in size and has ahigh degree of integration as described above in each of theembodiments. Accordingly, a reduction in size and an increase in thedegree of integration can be achieved in the electronic apparatus havingan imaging function.

The present technique can also be in the following forms.

(1)

A solid-state imaging device including:

-   -   a photoelectric conversion unit;    -   a transfer gate that reads out charges from the photoelectric        conversion unit;    -   a floating diffusion from which the charges of the photoelectric        conversion unit are read by an operation of the transfer gate;        and    -   an amplifying transistor of a fully-depleted type that is        connected to the floating diffusion.

(2)

The solid-state imaging device of (1), wherein the channel portion ofthe amplifying transistor is formed with an intrinsic semiconductor.

(3)

The solid-state imaging device of (1) or (2), wherein the amplifyingtransistor includes: convex strips formed by processing a surface layerof a semiconductor layer; and a gate electrode on the semiconductorlayer, the gate electrode extending in a direction perpendicular to theconvex strips.

(4)

The solid-state imaging device of (3), wherein

-   -   the convex strips are arranged in parallel, and    -   the gate electrode extends in the direction perpendicular to the        convex strips.

(5)

The solid-state imaging device of any of (1) through (4), wherein

-   -   the photoelectric conversion unit is located in the        semiconductor layer,    -   the transfer gate is located on a sidewall of a concave portion        formed by processing the surface layer of the semiconductor        layer along the photoelectric conversion unit, and    -   the floating diffusion is located at a bottom portion of the        concave portion.

(6)

The solid-state imaging device of (5), wherein

-   -   the amplifying transistor includes:    -   convex strips formed by processing a surface layer of the        semiconductor layer; and a gate electrode on the semiconductor        layer, the gate electrode extending in a direction perpendicular        to the convex strips, and    -   the steps formed by the concave portion are equal in height to        the steps formed by the convex strips.

(7)

The solid-state imaging device of any of (1) through (4), wherein

-   -   the photoelectric conversion unit includes:    -   an exposed-type photoelectric conversion unit formed in a        surface layer of the semiconductor layer; and    -   an embedded-type photoelectric conversion unit that is buried in        the semiconductor layer in such a manner as to be stacked on the        exposed-type photoelectric conversion unit, and faces the bottom        face of a concave portion formed in the semiconductor layer, and    -   the floating diffusion includes:    -   a floating diffusion that is formed in a surface layer of the        semiconductor layer and is located close to the exposed-type        photoelectric conversion unit, and    -   a floating diffusion that is formed in a bottom face layer of        the concave portion and is located close to the embedded-type        photoelectric conversion unit.

(8)

The solid-state imaging device of (7), wherein

-   -   the amplifying transistor includes:    -   convex strips formed by processing a surface layer of the        semiconductor layer; and    -   a gate electrode on the semiconductor layer, the gate electrode        extending in a direction perpendicular to the convex strips, and    -   the steps formed by the concave portion are equal in height to        the steps formed by the convex strips.

(9)

The solid-state imaging device of (7) or (8), wherein a photoelectricconversion unit formed with a photoelectric conversion film is placed onthe reverse face of the semiconductor layer while being stacked on thephotoelectric conversion unit.

(10)

A solid-state imaging device including:

-   -   a semiconductor layer having a concave portion formed therein;    -   a photoelectric conversion unit formed in the semiconductor        layer along a sidewall of the concave portion;    -   a transfer gate formed on the sidewall of the concave portion        along the photoelectric conversion unit; and    -   a floating diffusion that is formed to face a bottom portion of        the concave portion.

(11)

The solid-state imaging device of (10), wherein the transfer gateextends from the sidewall of the concave portion to the bottom portionof the concave portion.

(12)

The solid-state imaging device of (10) or (11), wherein the transfergate extends from the surface of the semiconductor layer to a sidewallof the concave portion.

(13)

A solid-state imaging device manufacturing method including:

-   -   forming convex strips by processing a surface layer of a        semiconductor layer;    -   forming a photoelectric conversion unit in the semiconductor        layer;    -   forming a floating diffusion in the surface layer of the        semiconductor layer, the floating diffusion being located close        to the photoelectric conversion unit; and    -   forming a transfer gate on the surface of the semiconductor        layer between the photoelectric conversion unit and the floating        diffusion, and a gate electrode connected to the floating        diffusion, the gate electrode extending in a direction        perpendicular to the convex strips.

(14)

The solid-state imaging device manufacturing method of (13), wherein

-   -   the forming the convex strips includes forming a concave portion        on the surface side of the semiconductor layer, the concave        portion forming steps having a height equal to the height of the        convex strips,    -   the forming the photoelectric conversion unit includes forming a        photoelectric conversion unit at a location along a sidewall of        the concave portion in the semiconductor layer, and    -   the forming the floating diffusion includes forming a floating        diffusion facing a bottom portion of the concave portion.

(15)

The solid-state imaging device manufacturing method of (14), wherein thetransfer gate is formed on the sidewall of the concave portion along thephotoelectric conversion unit.

(16)

The solid-state imaging device manufacturing method of (13), wherein

-   -   the forming the convex strips includes forming a concave portion        on the surface side of the semiconductor layer, the concave        portion forming steps having a height equal to the height of the        convex strips,    -   the forming the photoelectric conversion unit includes forming a        photoelectric conversion unit at a location along a sidewall of        the concave portion in the semiconductor layer, and a        photoelectric conversion unit at such a location as to be        stacked on the photoelectric conversion unit, and    -   the forming the floating diffusion includes forming a floating        diffusion in a surface layer of the semiconductor layer, and a        floating diffusion at a location facing the bottom portion of        the concave portion.

(17)

An electronic apparatus including:

-   -   a photoelectric conversion unit;    -   a transfer gate that reads out charges from the photoelectric        conversion unit;    -   a floating diffusion from which the charges of the photoelectric        conversion unit are read by an operation of the transfer gate;    -   an amplifying transistor of a fully-depleted type that is        connected to the floating diffusion; and    -   an optical system that guides incident light to the        photoelectric conversion unit.

REFERENCE SIGNS LIST

1, 1-1, 1-2 . . . Solid-state imaging device, 11 . . . Semiconductorlayer, 31 . . . Concave portion, 33 . . . Convex strips, 51 . . .Photoelectric conversion film (photoelectric conversion unit), 93 . . .Optical system, 90 . . . Electronic apparatus, AG . . . Amplifier gate(gate electrode), FD, FD1, FD2, FD3 . . . Floating diffusion, PDPhotodiode (photoelectric conversion unit), PD1 . . . Exposedphotodiode, PD2 . . . Embedded photodiode (photoelectric conversionunit), TG, TG1, TG2, TG3 . . . Transfer gate, Tr3 . . . Amplifyingtransistor

What is claimed is:
 1. A light detecting device comprising: asemiconductor substrate comprising a concave portion, the concaveportion comprising a side portion and a bottom portion; a photoelectricconversion region disposed in the semiconductor substrate; a firstsemiconductor region disposed in the semiconductor substrate, the firstsemiconductor region facing the bottom portion of the concave portion;and a transfer gate disposed on a side portion of the concave portionthrough a gate insulating film, the transfer gate being configured totransfer a charge in the photoelectric conversion region to the firstsemiconductor region.
 2. The light detecting device according to claim1, wherein the transfer gate extends from the side portion of theconcave portion to the bottom portion of the concave portion.
 3. Thelight detecting device according to claim 1, wherein the transfer gateextends from a surface of the semiconductor layer to the side portion ofthe concave portion.
 4. The light detecting device according to claim 1,wherein the first semiconductor region is a floating diffusion.
 5. Thelight detecting device according to claim 1, wherein at least a firstpart of the photoelectric conversion region is disposed above the firstsemiconductor region.
 6. The light detecting device according to claim5, wherein at least a second part of the photoelectric conversion regionis disposed below the first semiconductor region.